1. Field of the Invention
The present invention relates to semiconductor fabrication equipment, and more particularly, the present invention relates to improved semiconductor processing chamber electrodes and methods for making and implementing the improved electrodes.
2. Description of the Related Art
In semiconductor fabrication, integrated circuit devices are fabricated from semiconductor wafers that are placed through numerous processing operations. Many of the numerous processing operations are commonly carried out in processing chambers in which layers, such as, dielectric and metallization materials are successively applied and patterned to form multi-layered structures. For example, some of these layers (e.g., SiO.sub.2) are commonly deposited in chemical vapor deposition (CVD) chambers, and then photoresist materials are spin-coated and placed through photolithography patterning. When a photoresist mask is defined over a particular surface, the semiconductor wafer is placed into a plasma etching chamber in order to remove (i.e., etch) portions of the underlying materials that are not covered by the photoresist mask.
FIG. 1A shows a semiconductor processing system 100 including a chamber 102 that is used for processing semiconductor wafers through etching operations. In this example, the chamber 102 includes a chuck 104 which is configured to support a semiconductor wafer 106. The chuck 104 also supports a plurality of quartz rings 108. Over a topmost quartz ring 108, sits a ceramic ring holder 110, which is configured to hold a top electrode 114. The top electrode 114 is configured to receive processing gases which will be distributed into the plasma region 112 during processing.
The top electrode is also shown coupled to a match box and diplexer 116a and an RF power source 118a. The chuck 104 is also coupled to a match box and diplexer 116b and an RF power source 118b. The chamber 102 is provided with outlets 120 which are configured to pump out excess gases from within the chamber during processing. In operation, the RF power supply 118a is configured to bias the top electrode 114 and operate at frequencies of about 27 MHz. The RF power source 118a is primarily responsible for generating most of the plasma density within the plasma region 112, while the RF power source 118b is primarily responsible for generating a bias voltage within the plasma region 112. The RF power source 118b generally operates at lower frequencies in the range of about 2 MHz.
FIG. 1B provides a more detailed view of the top electrode 114 of the semiconductor processing system 100. The top electrode 114 generally includes a number of gas buffer plates 122 which have a plurality of holes defined throughout their surface region, and are configured to evenly distribute the processing gases throughout the top electrode 114. In this manner, the gas buffer plates 112 will ensure that an about equal amount of gas is allowed to flow out of each of the gas feed holes 128 of a silicon plate 126. The top electrode 114 also has a graphite ring 124 which is configured to mount onto the ceramic holders 110 of FIG. 1A. Once the process gases are allowed to flow out of the gas feed holes 128, a plasma may be generated in the plasma region 112 that is defined between the surface of the silicon plate 126 and a surface of the wafer 106.
During operation, the RF power 118a and the RF power 118b is applied to the top electrode 114 and the chuck 104, respectively. Once the process gases are channeled into the top electrode 114 and allowed to flow out of the gas feed holes 128 into the plasma region 112, a plasma sheath 131 and 132 will be defined within the plasma region 112 as shown in FIG. 1C.
As pictorially shown, the silicon plate 126 will have an electrode surface 134 which is directly opposite a wafer surface 136 of the semiconductor wafer 106. As is well understood in plasma physics, the electrode surface 134 and the wafer surface 136 are partially responsible for producing the plasma sheaths 131 and 132 within the plasma region 112.
Specifically, as shown in FIG. 1D, plasma sheaths edges are defined at points 133a and 133b along a plasma density profile 133. The plasma density profile illustrates that the plasma concentration falls to about zero near the wafer surface 136 and the top electrode surface 134. As such, the plasma concentration gradually increases from zero up to a constant concentration between points 133a and 133b. The electrode surface 134 and the wafer surface 136 will therefore ensure that the bulk of the plasma is contained between the plasma sheaths 131 and 132 as shown in FIG. 1C.
As the demand to etch smaller and smaller integrated circuit device patterns continues to increase, more difficult high aspect ratio etching will be needed. As shown in FIG. 1E, a cross sectional view 140 of a wafer substrate 106' is shown. The wafer substrate 106' has a dielectric layer 140 deposited thereon and a patterned photoresist layer 142. The photoresist layer 142 has a patterned window 144 defining a window down to the dielectric layer 140. As the aspect ratios continue to increase (i.e., deeper and narrower etching geometries), a process window that defines a set of controllable process parameters will also rapidly shrink. When the process window shrinks, adjustment of process parameters will no longer improve etch rates, etch selectivities, or etch profiles.
Typically, the process parameters include pressure settings, flow rates, electrode biasing powers, types of processing chemistries, and so on. However, as aspect ratios continue to increase, varying the process window parameters no longer assist a processing chamber's ability to control a desired etching operation. For example, when a geometry such as that defined by the patterned window 144 (i.e., for a contact via or the like) in the photoresist layer 142 is desired, the best etching chemistries may no longer be able to etch all the way down through the dielectric layer 140. When that happens, a premature etch stop 146 will develop because the processing chemistries will also be depositing polymers on the sidewalls and the bottom during the etching operation. As is well known, this polymer deposition can seriously retard the etching of dielectric layers 140 when high aspect ratio patterns are the subject of etching.
In efforts to combat this problem, process engineers have in the past, attempted to increase the level of oxygen within the processing chamber during an etch operation. Unfortunately, when the oxygen level is increased within the processing chamber, the etching operation will produce a bow-shaped etch 148 within the dielectric layer 140. As can be appreciated, when such a bow-shaped etch 148 occur within the dielectric layer 140, subsequent filling of the via hole defined by the bow-shaped etch 148 will be problematic. That is, conventional conductive fill techniques used to deposit metallization within a via hole may not work because of the bow-shaped etch via 148. As a result, a fabricated device having the bow-shaped etch via holes 148 may fail to function within its intended design.
Another solution attempted in the prior art has been to increase the bias power of the RF power source 118b that is coupled to the chuck 104 in an attempt to increase the ion bombardment energy over the surface of the wafer 106. However, when the bias voltage of the RF power source 118b is increased, more plasma is also generated within the plasma region 114, which counteracts the increase in ion bombardment energy. In addition, the processing molecules channeled into the plasma region 112 may change their chemical composition when the bias power is increased, and therefore, may fail to perform the desired etching. Consequently, it has been observed that merely increasing the RF power that is applied to the chuck 104 does not help in improving the etching of high aspect ratio geometries.
In view of the foregoing, what is needed is a processing apparatus and method for making and implementing the apparatus which will assist in increasing the ion bombardment energy at the surface of a wafer without also increasing the plasma density or changing the chemical composition of the processing molecules.